IBIS Macromodel Task Group Meeting date: 07 Aug 2012 Members (asterisk for those attending): Agilent: * Fangyi Rao * Radek Biernacki Altera: David Banas Julia Liu Hazlina Ramly Andrew Joy Consulting: Andy Joy Ansys: Samuel Mertens * Dan Dvorscak * Curtis Clark Steve Pytel Arrow Electronics: Ian Dodd Cadence Design Systems: Terry Jernberg * Ambrish Varma Feras Al-Hawari Cavium Networks: Johann Nittmann Celsionix: Kellee Crisafulli Cisco Systems: Ashwin Vasudevan Syed Huq Ericsson: Anders Ekholm IBM: Greg Edlund Intel: * Michael Mirmak Maxim Integrated Products: Mahbubul Bari Mentor Graphics: * John Angulo Zhen Mu * Arpad Muranyi Vladimir Dmitriev-Zdorov Micron Technology: * Randy Wolff * Justin Butterfield NetLogic Microsystems: Ryan Couts Nokia-Siemens Networks: * Eckhard Lenski QLogic Corp. * James Zhou Sigrity: Brad Brim Kumar Keshavan Ken Willis SiSoft: * Walter Katz Todd Westerhoff Doug Burns * Mike LaBonte Snowbush IP: Marcus Van Ierssel ST Micro: Syed Sadeghi Teraspeed Consulting Group: Scott McMorrow * Bob Ross TI: Casey Morrison Alfred Chong Vitesse Semiconductor: Eric Sweetman Xilinx: * Mustansir Fanaswalla * Ray Anderson The meeting was led by Arpad Muranyi ------------------------------------------------------------------------ Opens: - Mike: Having trouble with eda.org email reflector - Please send email to ibis-macro@freelists.org, ibis -------------------------- Call for patent disclosure: - None ------------- Review of ARs: - Arpad prepare example BIRD 125 IBIS file set - not done - Bob to propose a simpler way for addressing the needs of parameter passing under [External Model] and [External Circuit] - not done ------------- New Discussion: Walter showed a presentation "IBIS-ISS Package Modeling": - slide 1 to 3 are overview slides - slide 4: - Walter: Aggressor channels may be less accurate than victim, but must model crosstalk well - slide 5: - Walter: Drivers are on the same chip for FEXT - slide 6: - Walter: Banks imply associations between groups of buffers - slide 7: - Walter: The syntax used here is mostly to highlight the required functionality - Some materials are from vendors who can not be named, some can - slide 8: - Walter: Voltage supplies can have one name but multiple nodes - May need to support resistors in package - There is some redistribution of power and ground pin to pin - [Pin Mapping] may have some overlap, need to investigate - Alternative is to add Pullup_Signal_Name and Pulldown_Signal_Name - Arpad: It may be wise to stay away from [Pin Mapping] for new package syntax - Walter: That may be a rat hole - slide 9: - Walter: Cdie and Rdie may not represent the interconnect complexity well enough - slide 10: - Walter: This shows how the syntax might work together - Slide 11: - Walter: Die names here could be called "implicit" - X and Y coordinates are added to support MCP - Not fully advocating this feature - Fangyi: What are the units? - Walter: It is given here as "inch", but it could be microns for silicon - slide 12: - Walter: Supply die data are given separately here - These are explicit die names - slide 14: - Walter: Both implicit and explicit die names are used here - On-die models are assigned by name - Ports are listed in the order they appear in ISS - slide 15: - Walter: The package model example here passes Length in as a parameter - slide 16: - Walter: Pin names here are the high pins of diff pairs - This should cover 99% of package usage - slide 17: - Walter: This should handle 90% of package model cases - slide 18: - Walter: VDD and VSS are used to denote associated supplies - slide 19: - Walter: Not sure if this section about resistors is correct yet - slide 20: - Walter: This has 2 DQ aggressors and 1 DQS aggressor - The model name for the NEXT aggressor is given - DDR3 models tend to give values from standards, not what the part does - Fangyi: Is this saying where crosstalk is coming from? - Walter: The industry requires the aggressor and victim models to be the same - slide 21: - Walter: Some vendors want to supply more than 3 corners - This uses the {squiggly bracket} substitution syntax - slide 22: - Walter: It would be convenient to just use a Touchstone file, if that is all that is needed - slide 23: - Walter: Some models will describe a whole interface - Some terminals may not be correct in this example - slide 23: - Walter: Some models will describe a whole package - NC is used to leave some ports unconnected - Reduced s-param models can be derived from larger ones - slide 24: - Walter: They should be organized by sij instead of frequency to make it easier - slide 25: - Walter: A Perl script can produce the derived parameter syntax - slide 27: - Walter: Everything for package models can be used for on-die models - slide 28: - Walter: There are a few errors in this example - Slides 29 & 30: - Walter: These show an example for banks - Any number of voltage supplies can be passed in - slide 31: - Walter: I have tried to cover everything that others have requested - Is anything else required? - Do we need all that is here? - James: All signals are point to point, that should be a category - People want to see coordinates because we get power models with just one node name for all - Need to regroup into different quadrants - Walter: A connection could have just one supply name and several bumps - James: Are the victim features a superset of the aggressor features? - Walter: Correct - Arpad: Are the different examples using the same syntax? - Walter: An interface model is different - Only the victim channel is valid - Only that one has all the crosstalk modeled - Aggressors only generate noise - The syntax for them is different - The port order has "Pin" and "Pad" notation, for example - For interface models have actual pin and bump numbers - In interface models everyone is both victim and aggressor - Fangyi: In victim models you need to say which channel is valid - Walter: The ones with reserved names are the victims - Fangyi: We should be able to quickly identify which models are aggressor - Walter: That is a constraint of the person generating the subckt - Fangyi: Why specify aggressors? - Walter: They appear at a certain point in the subckt port order - There may be better ways to give this information - Arpad: This should be done in a more general way - Fangyi: You may want to analyze only 1 of 100 channels, and only a few neighbors matter - Walter: We need to know the pin and pad of each victim and aggressor - James: Pad is on the die side? - Walter: Pin is pin name and pad is bump pad - We need a consistent naming convention - Arpad: Using the P side of diff pairs only works if names are sequential - Walter: The [Diff Pin] section gives the other side ------------- Next meeting: 14 Aug 2012 12:00pm PT Next agenda: 1) Task list item discussions ------------- IBIS Interconnect SPICE Wish List: 1) Simulator directives